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l6246 12v voice coil motor driver 12v ( 10%) operation 3a maximum current capability 0.3 w maximum on resistance of each power dmos at a junction tem- perataure of 25c class ab power amplifiers logic and power supply monitor power on reset parking function with selectable retract voltage and dynamic brake before parking enable function gate driver for external blocking n-mosfet overtemperature protection overtemperature warning output pqfp44 package description the voice coil driver l6246 is a linear power am- plifier designed to drive single phase bipolar dc motors for hard disk drive applications. the de- vice contains a selectable transconductance loop, which allows high precision for head positioning. the power stage is composed of 2 power amplifi- ers, in ab class, with 4 dmoss, with rdson of 0.5 w (sink+source) maximum, in a h-bridge con- figuration. drive voltage for the upper dmos fets is provided by a charge pump circuit to en- sure low rdson. automatic brake and parking of the head actuator is performed by logic or when a failure condition is detected by power supply monitors. an external resistor programs the parking voltage that en- ables the head retract. in addition, a 5v stable output is provided for the external usage, and a gate driver circuit enables an external power sup- ply isolation n-mosfet. this device is built in bcd ii technology allowing dense digital circuitry to be combined with high power bipolar power devices and is assembled in pqfp44. august 2003 ? pqfp44 (10x10) multipower bcd technology 1/12
charge pump gate driver cp_gnd gate drive -spindle start motor start -w_gate -ae w_gate vcm park c1 c2 vcp thermal -thermal sd v cc +12 filter cap + - + - ref1 v dd +5 filter cap parking rpark ref1 vpark 10k 10k +5 4 m a 10k 30k 25k 20k v cc/2 err_out brake circuit + - + - + - + - v cc/2 error ampl. + - vbemf ref. volt. generator sense amplifier sense_ out sense _in- sense _in+ v cc/2 err- +5v ref +5v ref_gnd ref1 input amplifier vin- vin+ vin_out -por brake delay v cc out+ gnd v cc out- gnd d95in242b power amplifiers t_cap + - block diagram 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 sense-in- sense-in+ -thermal sd filter_cap n.c. brake delay n.c. sense-out err- gnd err-out vin_out vin- vin+ v cc/2 -ae_w_gate motor start v dd v cc -por +5v ref t_cap gate drive gnd out- v cc c2 vcp c1 v cc out+ gnd cpgnd rpark vbemf +12setpt +5v ref_gnd n.c. +5setpt n.c. enable -spindle start -w_gate vcm park d95in241b 12 13 14 15 16 pin connection (top view) l6246 2/12
absolute maximum ratings symbol parameter value unit v pow. max. maximum supply voltage 15 v v digital max. maximum supply voltage 7 v v in max. maximum input voltage v digital 0.3 v v in min. minimum input voltage gnd - 0.3 v i peak peak sink/source output current 3 a i dc dc sink/source output current 1.7 a p tot maximum total power dissipation @ 1.7 w t op operative temperature range 0 to 80 c thermal data symbol parameter value unit r th j-case thermal resistance junction to case @ 20 c/w r th j-amb thermal resistance junction to ambient mounted on standard pcb (*) @ 66 c/w r th j-amb thermal resistance junction to ambient mounted on pcb (**) @ 35 c/w (*) standard board construction: single layer (1s 0p); size 100mm long by 100mm wide. (**) the board construction includes: a 6 layer board (2s 4p, with power planes @ 80%); size 136mm long by 99mm wide; package location near middle point of lenght and one third of width. pin functions pin name description 1 n.c. not connected. 2 filter_cap filter capacitor for 10v internal regulator. the capacitor is optional. 3 brake delay voice coil motor brake delay capacitor. 4 -thermal sd pre thermal shut down indication output. 5 sense_in+ non inverting input of sense amplifier. 6 sense_in- inverting input of sense amplifier. 7 gnd ground. 8 err_out error amplifier output. 9 err- inverting input of error amplifier. 10 sense_out output of sense amplifier. 11 n.c. not connected. 12 vin_out output of input amplifier. 13 vin- inverting input of input amplifier. 14 vin+ non inverting input of input amplifier. 15 +vcc/2 half supply voltage reference. 16 +motor start motor start output to spindle controller. 17 -ae_w_gate write gate output to ae. 18 +vdd +5v supply. 19 +vcc +12v supply. 20 -por power on reset. low will s ignal the failure of the logic supply or 12v supply 21 +5v ref +5v reference output from the voltage reference regulator. 22 t_cap power on reset timing capacitor. the capacitor sets the por delay. 23 n.c. not connected. 24 +5v ref gnd ground for voltage reference generator. 25 +5setpt +5v monitor set point and filtering l6246 3/12
electrical characteristics (t j = 25c, vdd = 5v, vcc = 12v; unless otherwise specified.) symbol parameter test condition min. typ. max. unit vcc analog/power supply voltage range 10.8 12 13.2 v vdd digital supply voltage range 4.5 5 5.5 v idd digital supply quiescent current output enabled 5 ma idd digital supply quiescent current output disabled 5 ma icc power supply quiescent current output enabled 20 ma icc power supply quiescent current output disabled 10 ma thermal shut down data t h_sd shut down temperature 135 160 c t h_sd_h shut down hysteresys 25 c t h_warn pre shut down alarm 115 140 c pre shut down alarm hysteresys 15 c external n-mosfet gate driver vll low level voltage 500 mv vhl high level voltage vcc+4 v isink current sinking capability 4 ma isource current source capability 0.5 ma power on reset and gate specification v dd_und_th digital undervoltage threshold 3.8 4.1 4.45 v v cc_und_th power undervoltage threshold 8.5 9.25 10.0 v por _to por timeout cpor = 1 m f 375 500 625 ms por _delay time delay for por active 1 m s v dd_por_t_r power supply por thereshold resistance 10 k w pin functions (continued) pin name description 26 +12setpt +12v monitor set point and filtering 27 vbemf input bemf from spindle motor for parking circuit. 28 rpark resistor for setting the park voltage. 29 -w_gate write gate input. 30 +vcm park external input for parking. high will activate the park procedure. 31 -spindle_start spindle start input. 32 +enable input. logic low will disable only the ic. 33 n.c. not connected. 34 cpgnd charge pump ground. 35 gnd ground. 36 out+ power amplifier output. 37 vcc +12v power supply. 38 c1 charge pump oscillator output. 39 c2 input for external charge pump capacitor. 40 vcp output for charge pump storage capacitor. 41 vcc +12v power supply. 42 out- power amplifier output. 43 gnd ground. 44 gate drive gate drive for external isolation n-mosfets. l6246 4/12
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit v cc_por_t_r logic supply por thereshold resistance 10 k w i _por_o por output current drive 4 ma logic interface voltage level (all digital inputs are cmos compatible) voh cmos high level output voltage iout = 1.0ma 4.10 v vol cmos low level output voltage iout = 1.0ma 0.40 v vih ttl high level input voltage 2 v vil ttl low level input voltage 0.80 v 5v reference generator vref voltage reference at power on 4.75 5.00 5.25 v drift drift from power on -2 +2 % loref current output 10 ma input amplifier vi input voltage range vref (-) vref (+) v vcm input common mode voltage range 05.00v vds input differential voltage swing -5 +5 v vos input offset voltage -5 +5 mv ib input bias current -500 +500 na gv open loop voltage gain 80 db sr output slew rate 0.6 v/ m s gbw gain bandwidth product 1 mhz psrr power supply rejection ratio 80 db vo output voltage swing 9 v error amplifier vi input voltage range v cc /2 -0.5 v cc /2 +0.5 v vos input offset voltage -5 +5 mv ib input bias current -500 +500 na gv open loop voltage gain 80 db sr output slew rate 0.6 v/ m s gbw gain bandwidth product 1 mhz psrr power supply rejection ratio 80 db vo output voltage swing v cc /2 -2vbe v cc /2 +2vbe v sense amplifier vi input voltage range gnd vcc v vos input offset voltage -6 +6 mv ii input sink and source current -1.5 +1.5 ma psrr power supply rejection ratio 50 db gv vloltage gain 9.9 10 10.1 v/v rin differential input resistance 3 k w gbw gain bandwidth product 1 mhz vli linear differential input voltage range gv = 10(v/v) -0.35 +0.55 v cmrr common mode rejection ratio 56 db l6246 5/12
block description power amplifiers the two power amplifiers are connected in bridge configuration working in ab class. sense amplifier this stage senses the voltage drop across the rsense. the input stage is supplied by the charge pump voltage to have an high dynamic, while the other sections of the amplifier are supplied by the volt- age of 10.5v internally regulated to have an high power supply rejection (this voltage, supplies also the error amplifier, the input amplifier and the op- erational amplifier which generates the vcc/2 volt- age). the open loop gain is around 80db and the band- with is more than 1mhz. the voltage gain is fixed internally at 10 v/v. error amplifier this is the stage which compares the input volt- age and the sense voltage, generating the control voltage for the power section. the open loop gain and bandwith of this amplifier are similar to the sense amplifier. the negative input and the output of the error am- plifier are accessible externally in order to have the current loop compensation user configurable. the dynamic of the output is limited at +/- 2vbe to have a faster response of the output voltage. input amplifier the inputs and the output pins are externally ac- cessible to have the possibility to configure the transconductance gain of the current control loop selecting the voltage gain of this amplifier. the open loop gain and bandwith of this amplifier are similar to the sense amplifier. reference voltage generator this block generates the two reference voltage vcc/2 and +5 vref . the vcc/2 voltage is used as reference by the current control loop. the +5vref is a very stable voltage generator that can be used as reference voltage of an exter- nal dac . electrical characteristics (continued) symbol parameter test condition min. typ. max. unit power amplifier rdson dmos on resistance at 25c 0.3 w gdv differential voltage gain 32 v/v iol output current leakage 500 m a sr output slew rate 0.4 v/ m s tsr saturation recovery time 5 m s gbw gain bandwidth product 100 khz retract vr max. retract voltage vcc shorted to gnd 300 mv vr max. retract voltage vcc normal 1 v charge pump cs storage capacitor 1 m f vs storage voltage vcc +4 v cp pump capacitor 0.2 m f retract truth table input input output output -retract +enable bridge enable +retract brake and retract 0 x 0 1 run 1110 disable 1000 l6246 6/12
power supply monitor this circuit monitors the logic supply (5v) and the power supply (12v) and activates the power on reset output (por) and the vcm park circuit. after both logic and power supply reach their nominal value a timing capacitor (t_cap) has to be charge before the por output change from low to high level. por delay = c v i where: c is the capacitor value connected at pin t_cap v is delta voltage that capacitor have to be charged (2.3v) i is the costant current charging the capacitor (4 m a typ.) at the two input pins, +12 filter cap and + 5 filter cap, can be connected two capacitors for filtering the noise on the power supply, avoid- ing in this case undesired commutations of the por signal because of some fast negative spikes on the line. brake and parking circuits the voice coil driver is switched into the parking condition through the vcm park input or when the por signal is low. in such condition immedi- ately the output stage turns on the two lower dmos of the power bridge to activate the brake of the voice coil motor. after a delay generated by the capacitor at the brake delay pin, only one of the two lower dmos stays on while the opposite half bridge is tristated. brake delay = c v i where: c is the capacitor value connected at pin brake delay v is delta voltage that capacitor have to be charged (3v) i is the costant current charging the capacitor (5 m a typ.) the parking voltage is then supplied by the parking circuit connected to the output that has been tristated. the value of such a voltage is set by connecting an external resistor between the rpark pin and ground. v r = vbandgap 10 4 rpark where: vr is the retract voltage for parking the heads vbandgap is the internal bandgap reference voltage of 1.4v rpark is value of the resistor connected at rpark pin the parking circuit takes the power supply from the spindle driver through the vbemf pin, so that in case of power fail the retract of the heads is possible using the rectified bemf voltage coming from the spindle motor. charge pump the charge pump circuit is used as a means of al- most doubling the power supply voltage (12v) in order to drive the upper dmos of the power bridge. the energy stored in the in the capacitor con- nected at vcp pin is also used to drive the gate of the external n-mosfet. gate driver this circuit provide the voltage driving the gate of the external isolation n-mosfet, and it is con- trolled by the por signal. thermal the thermal protection circuit has two threshold, the first if the pre shut down alarm that activates the thermal sd signal and the second is the shut down temperature that tristates the output stage when the junction temperature increases over this level. application information example of calculation of the error amplifier com- pansation for the stability of the current control loop. as can be seen from the draw of the current control loop circuit of the next page, the voltage across the load is: #1 v l = a cpw a cerr (a cinp v in - a cense v sense ) v sense = rs i l v l = ( z l + rs) i l where a c ... is the closed loop gain of power, er- ror, sense and input amplifier. changing in the #1 the transfer function between the load current and the v in is: #2 i l v in = a cpw a cerr a cinp z l + r s + a cpw a cerr a csense r s l6246 7/12
l6246 pqfp44 10 8 9 12 13 1k 100nf err- err_out sense_out 1m 1k 1k 10k vin_out vin- 14 vin+ 10k 10k 10k v cc/2 v ref v ctl 15 v cc/2 34 7,35,43 cpgnd gnd rs 0.2 ll rl voice coil motor out_ sense_in- sense_in+ out+ 42 6 5 36 v dd 100nf v dd 18 22 m f 100nf v cc v cc v cc v cc gate drv 19 41 37 44 27 g s d v bemf from spindle driver 100nf 40 28 r park v cp p322 1 m f 51k 26 12s ept (*) 25 5s sept (*) 10nf c1 c2 38 39 21 5v ref 24 5v ref gnd 5v ref gnd 22 12s ept 1 m f 3 5s sept 1 m f ae w gate motor start thermal shtd por 17 16 4 20 32 enable 30 vcm park 31 spindle start 29 w gate 2 filter_cap 10.5v int.reg. (*) d95in268 filter capacitors to be set in application typical application circuit 20k 2k 2k v cc/2 + 10v sense 20k v cc/2 v cc/2 sense ampl. r1 error ampl. - + rc (=r1) v cc/2 - (ra-rb) vin ra rb rb ra input ampl. - + r2 r3 c vin v sense v cc/2 17.5k 1.1k v cc/2 16.5k v cc/2 v cc/2 + (ra/rb) (z c /rc) vin-10 (z c /r1) v sense -+ r s rl ll load vl power ampl. power ampl. 1.1k z c vl=32 ( (zc/rc) vin - 10 (z c /r1) v sense ) = a cpw * a cerr ( a cimp * vin - a csense * v sense ) d95in269b to sense amplifier + - - + - + - + current control loop circuit l6246 8/12
if now we define: #3 aloop = a cpw a cerr a csense r s r s + z l we obtain: #4 i l v in = aloop a cinp a csense 1 r s 1 + a loop at low frequency is: aloop = 32 r2 r1 10 r s ( r s + z l ) if r2 = 1m, r1 = 1k, r s = 0.2, r l = 7 then aloop = 8889 = 80db. being aloop very high we can simplify the #4 in this way: i l v in = a cinp a csense 1 r s = 1 10 0.2 = 1 2 for the stability we have to study the stability of aloop, that as we can see from the #3 is a multi- plication, so in db is a sum: aloop | db = a cpw | db +a cerr | db +a csense | db + r s r s + z l ? db so we can take in consideration the bode dia- grams of the each operational amplifier, with par- ticular attention to the error amplifier. 1)the power amplifier is actually composed by two operational amplifiers in the way to have a gain of +16 and -16 (in voltage) respec- tevely, for a total of 32 = 30db. the point at -3db is around 130khz. 2)the sense amplifier has a gain of 20db with the point at -3db around 210khz. 3)the load introduce an attenuation of: 20log r s r s + r l = -31db with r s = 0.2 and r l = 7 and its pole is at frequency 1 2 p l ( r s + r l ) so around 1khz if l = 1.2mh . so considering: ax | db = aloop | db a cerr | db a cpw | db + a csense | db + r s r s + r l ? db we have these bode diagrams: as can be easily see the bandwith is narrow and the gain is low. it is possible to increase both choosing an appropriate compensation of the er- ror amplifier. the total bandwith should be, of course, at least a decade lower of the 130khz to avoid instability problem. the bandwith guaranteed by the error amplifier has a gmax of 80db and a gain of 0db at 1mhz approximately, the real is some db more with a larger bandwith. acpw 30db 130khz acsense 20db 210khz -31db load ax 19db 1k 10k 100k d95in270a l6246 9/12
using the compensation network of the draw of pag.8, we have a error amplifier transfer function of: v o v i = - zc r1 = - r2 r1 1 + scr3 1 + sc ( r3 + r2 ) so: gmax (dc) = r2 r1 = 1000 = 60db with r1 = 1m w and r2 = 1k w zero = 1 2 p r3c pole = 1 2 p ( r3 + r2 ) c note: fpole is lower than fzero the best choice is to cancel the pole of the load (at around 1khz) with the zero of the compensa- tion. as can be seen the choice of the pole influence overall in fixing the gain at high frequency. the gain at high frequency must be choosen in order to not create instability problem, because more higher is this gain and lower is the second pole that we have at high frequency. if this pole is taken close to the other that we have already seen at 130khz and 210khz, insta- bility problems can arise. adding together ax | db and a cerr | db we ob- taine the aloop: so the choice of the compensation network must be done in order to fix at the beginning the gmax of the error amplifier depending on the ratio r2 r1 . to calculate the r3 and c values satisfying the following system: 1 2 p r3c = 1 2 p l r l + r sense error amplifier zero equal to load pole 1 2 p ( r3 + r2 ) c = admissible bandwith gloop = = 130khz 10 8912 = 1.5hz this example is for crossing the 0db one decade before the first pole of the power amplifier (130khz), starting with a gloop max of 79db. error ampl. gain (db) 40 60 20 1k 10k 100k d95in271 100 120 80 1 10 100 1m 10m open loop gain acerr (db) 40 60 20 1k 10k 100k d95in272 100 120 80 1 10 100 1m 10m closed loop acerr x x differents poles examples x acerr (db) 20 compensation at 3hz ax(db) 19 d95in273 40 60 a loop (db) 20 40 60 79 10 100 1k 10k 100k 1m 10m compensation at 100hz is stable is not stable l6246 10/12
pqfp44 (10 x 10) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e3 d3 e1 e d1 d e 1 k b pqfp44 l l1 0.10mm .004 dim. mm inch min. typ. max. min. typ. max. a 2.45 0.096 a1 0.25 0.010 a2 1.95 2.00 2.10 0.077 0.079 0.083 b 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 d 12.95 13.20 13.45 0.51 0.52 0.53 d1 9.90 10.00 10.10 0.390 0.394 0.398 d3 8.00 0.315 e 0.80 0.031 e 12.95 13.20 13.45 0.510 0.520 0.530 e1 9.90 10.00 10.10 0.390 0.394 0.398 e3 8.00 0.315 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k0 (min.), 7 (max.) outline and mechanical data l6246 11/12
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com l6246 12/12

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